High-performance programmable processing element for GF (2N)

ABSTRACT

Many functions in communication require Galois Field (GF). With the given processing elements, any kind of Transfer Function can be realized. This therefore provides a very scaleable and flexible computational and processing architecture.

CROSS REFERENCE TO RELATED APPLICATION

[0001] I claim the benefit of the filing date of PPA 60/308,399 on Jul. 30, 2001.

FEDERALLY SPONSORED RESEARCH

[0002] Not Applicable

SEQUENCE LISTING OR PROGRAM

[0003] Not Applicable

BACKGROUND

[0004] 1. Field of the Invention

[0005] This invention relates to a scaleable and flexible Processing Element (PE) for GF (2^(n)) computations.

[0006] 2. Description of the Prior Art

[0007] High performance processing engines used in networking and communications applications are typically hard-wired. Software techniques are typically used when programmability/flexibility is required. Software approaches are inherently low performance whereas hardware approaches are inherently inflexible.

[0008] Instead of designing hard-wired circuits, this invention can be used to implement Encoding/Decoding, Forward Error Correction (FEC), Encrypt/Decrypt, Cyclic Redundancy Check (CRC), Scrambling and other types of GF (2^(n)) functions. The same PE can be time-shared to implement multiple functions. For example, the PE can be used to compute the header CRC for a packet header and, later, it can be configured to compute CRC for the packet payload.

SUMMARY OF INVENTION

[0009] This invention describes a single structure that can implement a variety of functions: CRC, scrambling, FEC, etc. It has programmable operations and can generate polynomials.

DRAWINGS DRAWING FIGURES

[0010] The construction designed to carry out the invention will hereinafter be described, together with other features thereof.

[0011] The invention will be more readily understood from a reading of the following specification and by reference to the accompanying drawings forming a part thereof, wherein an example of the invention is shown, and wherein:

[0012]FIG. 1 is a diagram of the GF (2^(n)) Functional Block

[0013]FIG. 2 is a diagram of A High Performance Programmable Processing Element for GF (2^(n)) Operations

[0014]FIG. 3 is a diagram of Tile T_(i)

REFERENCE NUMERALS IN DRAWINGS

[0015]  10 Execution Path  20 Controller  30 Control Process Interface  40 Serial Input  50 Serial Processors  60 Tile T_(N)  70 Tile T  80 Terminal Out  90 Terminal In 100 Generator Polynomial 110 Mode Control 120 Multiplexer 130 Shift Register 140 Exclusive OR Gate 150 AND Gate

DETAILED DESCRIPTION

[0016] Many Galois Field (GF) operations can be written in the form of matrix operations in GF (2^(n)). CRC, Block Codes, Scrambling, Random Number Generation are some of the examples of operations that may be represented in this manner. A programmable processing element for these operations can be designed in this manner. This leads to a potentially very expensive implementation.

[0017] Alternatively, it is possible to view these operations as bit serial operations based on shift registers. This leads to a simple implementation.

[0018] From the description above, a number of advantages of this invention become evident:

[0019] (a) Highly cost effective design.

[0020] (b) Much simpler to implement. 

We claim:
 1. Programmable elements which can program a family of galois field functions.
 2. A method of cascading programmable elements to realize complex transfer functions.
 3. A programmable architecture which provides performance of hard wired approach. 